1. Field of the Invention
The present invention relates to a semiconductor memory and, more particularly, to a static random access memory (SRAM) having a plurality of ports.
2. Description of the Related Art
In recent years, in a field of an image signal memory or the like, a plural port SRAM having at least one port capable of reading data from a dual or triple port SRAM cell having a plurality of ports regardless of other ports in a writing state or a reading state.
FIG. 1 shows a part of a conventional dual port SRAM. In this case, reference symbol Vcc denotes a power source potential (e.g., 5 V); Vss, a ground potential; MC, a dual port SRAM cell; Din1 and Din1, complementary write data of a first port; Din2 and Din2, complementary write data of a second data ; Dout1 and Dout1, complementary readout data of the first port; and Dout2 and Dout2, complementary readout data of the second port. A pair of complementary bit lines BL1 and BL1 of the first port and a word line WL1 of the first port are connected to an SRAM cell. The output terminals of write clocked inverters CV1 and CV1 of the first port and the input terminal of a CMOS current mirror type bit line sense amplifier CMSA1 of the first port are connected to the pair of bit lines BL1 and BL1 of the first port. A pair of complementary bit lines BL2 and BL2 of the second port and a word line WL2 of the second port are connected to an SRAM cell MC.
The output terminals of write clocked inverters CV2 and CV2 and the input terminal of a CMOS current mirror type bit line sense amplifier CMSA2 of the second port are connected to the bit lines BL2 and BL2 of the second port.
The write clocked inverters CV1 and CV1 of the first port are driven by an inversion control signal (R/W) 1 of the first port which is set at low level ("L") during a read operation and set at high level ("H") during a write operation. The write clocked inverters CV2 and CV2 are driven by an inversion control signal (R/W) 2 of the second port which is set at "L" level during a read operation and set at "H" level during a write operation.
The dual port SRAM cell MC is constituted as follows. That is, a flip-flop (comprising two load p-channel MOS transistors P1 and P2 and two drive n-channel MOS transistors N1 and N2 which are connected across each other) FF is connected between a Vcc power source and a ground terminal, and one terminal of each of a pair of n-channel MOS transistors T1 and T1 serving as transfer gates of the first port is connected to a corresponding one of a pair of input/output nodes N and N of the flip-flop FF. In addition, one terminal of each of a pair of n-channel MOS transistors T2 and T2 serving as transfer gates of the second port is connected to a corresponding one of the pair of input/ output nodes N and N of the flip-flop FF. The gates of the pair of n-channel MOS transistors T1 and T1 and are connected to the word line WL1 of the first port, and the other terminal of each of the pair of transistors T1 and T1 is connected to a corresponding one of the bit lines BL1 and BL1 the first port. The gates of the pair of n-channel MOS transistors T2 and T2 are connected to the word line WL2 of the second port, and the other terminal of each of the pair of transistors T2 and T2 is connected to a corresponding one of the pairs of BL2 and BL2 of the second port.
Therefore, in the dual port SRAM, a read/write operation by the first port and a read/write operation by the second port can be independently performed.
In the dual port SRAM with the above arrangement, during a write operation of the SRAM cell MC from the first or second port, the potential of the pair of bit lines BL1 and BL1 or the pair of BL2 and BL2 are changed from the ground potential to the power source potential Vcc. In this case, a large number of SRAM cells MC are connected to the pair of bit lines BL1 and BL1 and the pair of bit lines BL2 and BL2, and the pairs of bit lines have a large amount of parasitic capacitance. Therefore, since an SRAM cell MC selected during a read operation must charge/discharge the large amount of parasitic capacitance from the pair of bit lines BL1 and BL1 or the pair of bit lines BL2 and BL2, a time required for reading data is prolonged.
In a high-speed single port SRAM formed by a Bi (bipolar)--CMOS (complementary insulated gate type) technique, a method of decreasing a potential amplitude of a bit line during a read operation by a current sensing circuit in which a base ground circuit is connected to an input side of an emitter coupling bit line sense amplifier so as to reduce a read time delayed by the parasitic capacitance of the bit lines is disclosed in a literature (1989 SYMPOSIUM ON VLSI CIRCUITS, Digest of Technical Papers, pp. 67 to 68).
For this reason, the above current sensing circuit will be used as an arbitrary port of a plural port SRAM. However, in the plural port SRAM, when a read operation is performed from a port using the current sensing circuit during a write operation, a device in which the potential of the bit line using the current sensing circuit does not adversely affect the write operation must be developed.
As described above, according to a conventional plural port semiconductor memory, since a memory cell selected during a read operation must charge/discharge a large amount of parasitic capacitance of a pair of bit lines, a time required for reading data is enlarged.